Digital India RISC-V Symposium - A Tech Showcase For India's Future Electronics
Ministry of Electronics and Information Technology, IIT Madras and IITM Pravartak Technologies Foundation are collaborating to present the "Digital India RISC-V Symposium, a one-day event showcasing the future of Electronics" in India through the RISC-V pathway.
This Symposium will feature insightful tech talks by esteemed academicians and industry experts, interactive stalls showcasing indigenous RISC-V processors, an engaging hackathon, and a special Investor meeting. If you're seeking to break free from conventional approaches and create disruptive designs, this is the perfect opportunity for you.
Join us for an exploration of the present and future opportunities with RISC-V!
Date : August 6, 2023
Venue : New Auditorium, D7, D Block, IITM Research Park, Taramani, Chennai 600113
Time : 09:00 am Onwards
About Digital India RISC-V Symposium
The basic component of a processor is its ISA [Instruction set architecture]. It is known that all processors have both hardware and software. While the hardware part of the processing component is fundamentally dependent on physical elements such as gates, transistors, clocks, memory, interconnect peripherals, semiconductor technology nodes etc, the software development is highly inspired by the end-user application scenario. A processor’s ISA determines where and how this software and hardware meet and what the interface should be, and thus, the fundamental design of the processor itself.
Unlike the heavily stifling, proprietary closed and licensed ISA-based approach followed by other processors in the market, which usually targets general-purpose applications, RISC-V-based processor designs are inspired by domain-specific applications. RISC-V ISA license is free, open source, modular, addable, scalable, and customisable and thus can scale from processors for simple microcontrollers [for small embedded applications] to purpose-built Cyber-Physical Systems to tiny IOT/WSN devices to cloud computing platforms to High-Performance Computing systems for both scientific and ML training. RISC-V ISA is free and it enables a new era of processor innovation through open standard collaboration.
Digital India RISC-V Symposium
The GOI, taking the concrete steps towards realizing the ambition of self-reliance and a momentous stride towards “Atmanirbhar Bharat”, launched the Digital India RISC-V Microprocessor (DIR-V) Program with an overall aim to enable creation of Microprocessors for the future in India, for the world and achieve industry-grade silicon & Design wins by December'2023 For more details
Sensing this non-stifling enormous opportunity that can be leveraged by the startup-entrepreneurship initiatives, especially from the student community, the Digital India RISC-V Symposium is the first-in-line tech symposium focussing exclusively on RISC-V based product design road map and opportunities for Electronics in India.
Shri. Rajeev Chandrasekhar
Minister of State for Electronics and Information Technology,
Skill Development and Entrepreneurship Government of India.
To Register - Click here
Note : e-Certificate, welcome kit and lunch will be provided to the registered participants.